1. Field of the Invention
The present invention relates generally to phase-locked loops. Particularly, the invention relates to devices that minimize reference spurs from charge pumps used in phase-locked loops.
2. Discussion of Related Art
FIG. 1 shows a phase-locked loop (PLL) 100 including a phase detector 102, charge pump 104, loop filter 106, voltage controlled oscillator (VCO) 108, frequency divider 118, and reference divider 119.
VCO 108 outputs an oscillating signal, OUT 112, that is the output signal of PLL 100. The frequency of OUT 112 linearly corresponds to the voltage at the input of VCO 108. OUT 112 is fed to frequency divider 118 which divides the VCO frequency by a value N. The output signal of frequency divider 118 is fed back to phase detector 102, which compares the phase of OUT 112 to the phase of an input signal, equivalent to REF 110 divided by R by reference divider 119. When locked, the frequency of OUT 112 is the frequency of REF 110 times (N/R).
Phase detector 102 supplies two pulses that have a difference in duration proportional to the phase difference between the signal output from reference divider 114 and the signal output from frequency divider 118. For example, when the phase of OUT 112 divided by N lags the phase of REF 110 divided by R, the frequency of OUT 112 is increased by increasing the voltage at the loop filter 106. This voltage increase is achieved by supplying charge pump 104 a pulse of inverted UP 114 that has a duration longer than DN 116. When the frequency of OUT 112 divided by N is greater than that of REF 110 divided by R, phase detector 102 supplies DN 116 that is longer in duration than inverted UP 114.
Charge pump 104 responds to pulses of inverted UP 114 and DN 116 by outputting a current to loop filter 106, which often includes a large capacitor. The output signal of loop filter 106 is averaged to define a DC voltage at the input terminal of VCO 108. Charge pump 104 responds to pulses of inverted UP 114 by outputting positive current pulses that add charge to the capacitor of loop filter 106, raising the DC voltage at the input of VCO 108. Charge pump 104 responds to pulses of DN 116 by outputting negative current pulses that remove charge from the capacitor of loop filter 106, lowering the DC voltage at the input of VCO 108. Therefore, the difference in duration between inverted UP 114 and DN 116 is proportional to the net charge injected into loop filter 106. When the frequency of OUT 112 divided by N is equal to the frequency of REF 110 divided by R, PLL 100 is "in lock". When "in lock", the DC voltage of loop filter 106 is constant and no net charge should be injected into loop filter 106.
To ensure the smallest instantaneous disturbance of the voltage input to loop filter 106, phase detector 102 is often designed so that inverted UP 114 and DN 116 terminate at the same time.
As shown in FIG. 2, charge pump 104 consists of two current sources: up current source 202 and down current source 204. The pulses of inverted UP 114 and DN 116 described earlier control the current sources, 202 and 204, respectively. When the PLL is in lock, the duration of inverted UP 114 and DN 116 should be identical. Consequently, the two currents should be equal ("matched"), i.e., the current in up current source 202 should equal the current in down current source 204.
In a "charge pump" event occurring at frequency F, corresponding to the operating frequency of charge pump 104, charge pump 104 periodically adjusts the voltage input to VCO 108, and consequently the frequency of OUT 112. Despite the PLL being in lock, a mismatch in the instantaneous currents of current sources 202 and 204 may still occur. FIG. 3A depicts a potential mismatch between currents I.sub.up and -I.sub.dn of up current source 202 and down current source 204, respectively, due to finite output impedance of the current sources. FIG. 3B depicts the instantaneous charge induced into loop filter 106 by the current mismatch depicted in FIG. 3A. DN 116 has slightly longer duration to compensate for the reduced magnitude of -I.sub.dn, so that the net charge injected into the loop filter remains zero. At the conclusion of the charge pump event, the net charge added to the loop filter is zero.
FIG. 4 shows the energy spectrum of the charge pump event shown in FIGS. 3A and 3B. As shown in FIG. 4, the addition and subtraction of charge depicted in the example of FIG. 3B causes power "spurs" 300 ("spurious tones") that occur at a distance equal to multiples of the charge pump's operating frequency F on both sides of the frequency of OUT 112.
When the PLL is in lock, spurs are undesired. In communications systems, spurs may cause undesired distortions of signals and mixing with adjacent channels.
A solution to the spur problem was to design a charge pump with tolerable mismatch in currents during lock. However, because the output impedance of current sources in charge pumps is finite, current mismatch always occurred between the current supplies when the loop filter voltage is changed. So, a range of loop filter voltages established where the magnitude of the spurs were tolerable. However, the PLL was limited in output operating frequency range (tuning range) by the presence of spurious tones.